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Timing Predictability in Future Multi-Core Avionics Systems

機(jī)譯：未來(lái)多核航空電子系統(tǒng)中的時(shí)間可預(yù)測(cè)性

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摘要

With more functionality added to safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core platforms offer a potential that is now being explored, but they pose significant challenges with respect to predictability due to shared resources (such as memory) being accessed from several cores in parallel. Multi-core processors also suffer from higher sensitivity to permanent and transient faults due to shrinking transistor sizes. This thesis addresses several of these challenges. First, we review major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. In particular, works that evaluate the timing effects using fault injection methods. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with the fault tolerance techniques. We assess the applicability of the methods to COTS multi-core processors used in avionics. We identify dark spots on the research map of the joint problem of hardware reliability and timing predictability for multi-core avionics systems. Next, we argue that the memory requests issued by the real-time operating systems (RTOS) must be considered in resource-monitoring systems to ensure proper execution on all cores. We also adapt and extend an existing method for worst-case response time analysis to fulfill the specific requirements of avionics systems. We relax the requirement of private memory banks to also allow cores to share memory banks.
機(jī)譯：隨著對(duì)安全性至關(guān)重要的航空電子系統(tǒng)增加了更多功能，需要新平臺(tái)來(lái)提供所需的計(jì)算能力。多核平臺(tái)提供了正在探索的潛力，但是由于要從多個(gè)核并行訪問共享資源（例如內(nèi)存），因此它們?cè)诳深A(yù)測(cè)性方面提出了重大挑戰(zhàn)。由于晶體管尺寸的縮小，多核處理器對(duì)永久性和瞬態(tài)故障的敏感性也更高。本文解決了其中一些挑戰(zhàn)。首先，我們回顧了主要貢獻(xiàn)，這些貢獻(xiàn)評(píng)估了容錯(cuò)能力對(duì)在多核平臺(tái)上運(yùn)行的進(jìn)程的最壞情況執(zhí)行時(shí)間的影響。特別是使用故障注入方法評(píng)估時(shí)序影響的作品。我們得出的結(jié)論是，很少有工作可以解決由于共享資源的同時(shí)訪問而導(dǎo)致的核心間干擾與容錯(cuò)技術(shù)結(jié)合使用時(shí)出現(xiàn)的復(fù)雜時(shí)序影響。我們?cè)u(píng)估了該方法對(duì)航空電子中使用的COTS多核處理器的適用性。我們?cè)诙嗪撕娇针娮酉到y(tǒng)的硬件可靠性和定時(shí)可預(yù)測(cè)性聯(lián)合問題的研究圖上發(fā)現(xiàn)了黑點(diǎn)。接下來(lái)，我們認(rèn)為必須在資源監(jiān)視系統(tǒng)中考慮由實(shí)時(shí)操作系統(tǒng)（RTOS）發(fā)出的內(nèi)存請(qǐng)求，以確保在所有內(nèi)核上正確執(zhí)行。我們還調(diào)整并擴(kuò)展了用于最壞情況響應(yīng)時(shí)間分析的現(xiàn)有方法，以滿足航空電子系統(tǒng)的特定要求。我們放寬了對(duì)專用存儲(chǔ)體的要求，以允許內(nèi)核共享存儲(chǔ)體。

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  • 作者

    L?fwenmark, Andreas;

  • 作者單位
  • 年度 2017
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  • 原文格式 PDF
  • 正文語(yǔ)種 eng
  • 中圖分類

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